As feature sizes have become smaller and multilevel metallization commonplace in integrated circuits, low dielectric constant films have become increasingly important. Low dielectric constant films are particularly desirable for intermetal dielectric (IMD) layers to reduce the RC time delay of the interconnect metallization being covered, to prevent crosstalk between the different levels of metallization, and to reduce device power consumption.
Sub-half micron multilevel metallization is one of the key technologies for the next generation of very large scale integration (“VLSI”). The multilevel interconnects that lie at the heart of this technology require planarization of high aspect ratio features such as plugs and other interconnects. Reliable formation of these interconnects is very important to the success of VLSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Conventional chemical vapor deposition (CVD) and physical vapor deposition (PVD) techniques are used to deposit electrically conductive material into the contact holes, vias, trenches, or other features formed on the substrate. One problem with conventional processes arises because the contact holes or other patterns often comprise high aspect ratios, i.e., the ratio of the height of the holes to their width or diameter is greater than 1. The aspect ratio of the holes increases as advances in technology yield more closely spaced features.
The presence of native oxides and other contaminants within a small feature typically results in voids in the metal deposited in the features as the native oxides and other contaminants promote uneven distribution of the depositing metal. The native oxide typically forms as a result of exposing the exposed film layer/substrate to oxygen. Oxygen exposure occurs when moving substrates in air between processing chambers at atmospheric conditions, or when a small amount of oxygen remaining in a vacuum chamber contacts the wafer/film layer, or when a layer is contaminated by etching. Other contaminants within the features can be sputtered material from an oxide over-etch, residual photoresist from a stripping process, leftover hydrocarbon or fluorinated hydrocarbon polymers from a previous oxide etch step, or redeposited material from a preclean sputter etch process. The native oxide and other contaminants create regions on the substrate which interfere with film formation, by creating regions where film growth is stunted. Regions of increased growth merge and seal the small features before regions of limited growth can be filled with the depositing metal.
The presence of native oxides and other contaminants also can increase the via/contact resistance and can reduce the electromigration resistance of small features. The contaminants can diffuse into the dielectric layer, the sublayer, or the deposited metal and alter the performance of devices which include the small features. Although contamination may be limited to a thin boundary region within the features at the interface of the deposited metal and an underlying conductive or semi-conductive feature, the thin boundary region is a substantial part of the small features. The acceptable level of contaminants in the features decreases as the features become smaller in width.
Precleaning of features using sputter etch processes is effective for reducing contaminants in large features or in small features having aspect ratios smaller than about 4:1. However, sputter etch processes can damage silicon layers by physical bombardment, sputter deposition of Si/SiO2 onto sidewalls of the features, and sputter deposition of metal sublayers, such as aluminum, onto sidewalls of the features. For larger features, the sputter etch processes typically reduce the amount of contaminants within the features to acceptable levels. For small features having larger aspect ratios, sputter etch processes have not been as effective in removing contaminants within the features, thereby compromising the performance of the devices which are formed.
Referring to FIG. 1, a substrate 10 including a hole 11 formed within an electrically insulative or dielectric layer 12 thereon, such as for example, a silicon dioxide or silicon nitride layer is shown. It is difficult to deposit a uniform metal-containing layer into the high aspect ratio hole 11 because contaminants on the sidewalls 14 of the holes promote uneven deposition of the metal containing layer. The metal containing layer eventually converges across the width of the hole before it is completely filled, thus forming voids and discontinuities within the hole. Thereafter, the high mobility of metal atoms surrounding the voids causes the atoms to diffuse and minimize the surface area of the voids forming circular shaped voids as shown in FIG. 1. These voids and discontinuities result in poor and unreliable electrical contacts.
Precleaning is primarily a sputter etch type process, wherein contaminants are sputtered from the substrate. It is preferably conducted with a mixture of an inert gas, typically argon, and a reactive gas, typically hydrogen. Mixtures of argon and hydrogen remove both reactive and non-reactive contaminants and can be used to modify the shape of contact holes, vias, trenches and other patterns to improve subsequent metal deposition processes. Increasing the argon content in the preclean mixture provides a corresponding increase in the etch rate of the preclean process and a corresponding decrease in the etch uniformity of the preclean process. Hydrogen must be included in the mixture to effectively remove reactive compounds or contaminants such as hydrocarbons. Precleaning patterned substrates with a mixture of argon and any amount of hydrogen provides a lower etch rate and an increased etch non-uniformity than precleaning with argon.
A preclean process having both high concentrations of reactive gases and improved etch rates would substantially promote removal of contaminants by addition of the reactive gases.
U.S. Pat. No. 5,660,682, by Zhao et al, illustrates an attempt to combine etching and reactive cleaning of patterned dielectric layers using a plasma comprising hydrogen and argon. The argon etches deposits from apertures and the hydrogen reacts with remaining deposits to form gaseous byproducts. The combination of etching and cleaning does improve subsequent deposition of metals, however, the combined plasma processing does not prevent formation of voids in subsequent metal layers. Therefore, there remains a need for a method to improve deposition of metal layers on a patterned dielectric layer, especially apertures such as vias and trenches having an aspect ratio greater than about 1.0.